The gain of 10 is about the maximum you would usually have without bypassing or partially by-passing the emitter resistance with a capacitor. The low Ve is a knock-on effect of having such a low load resistance combined with the high gain. The problems you have been experiencing are due to Vbe sensitivity which is caused by having such a low voltage at the emitter (56mV). The load regulation ratio for DC or gain is simply a function of the impedance ratio with output. Of course, the simplest solution is just define Rc as the load There are tradeoffs with any design and more specifications lead to better designs. 15% tolerances are expected even with 1% resistors in this design due to the load /Rc ratio. ( except no load gain = Rc/Re and loaded gain = 10 ). So I suggest you recalc R3 for a smaller Vbe and your design "may" work as expected. This adds more Ve and thus more Ic current to your design. The biggest source of error only in this case, is teachers always tell you to assume Vbe=0.7V but for Ic= 1mA it is very close to Vbe= 600 mV. Otherwise you will get asymmetrical limiting as the load pulls down the voltage more than Rc pulls upīut this is an unusually large Vcc, Low Ic * Load = 1V which limits your peak swing.Ģ% to 10 % tolerances are acceptable and hFE can be largely ignored. I am kind of stuck, I don't know where I made a mistake.Īlways choose Rc <= than Rload so that transistor is never starved of Ic current.
Problem is, when measuring the DC operating point of the collector current, I measure 1.6 mA instead of 1. Then I simulated the following circuit in LTspice:įor the gain, I obtain approximately 11.184 which is in the margin of error. So to fulfill these requirements, I made a system of equations to obtain the values of the resistances. I need to design a common emitter amplifier for my next electronics laboratory.įor 1mA, $$ \beta = 185 $$ according to the datasheet.
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